MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1250

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory map and register definition
45.4.4 Transfer Type Register (SDHC_XFERTYP)
This register is used to control the operation of data transfers. The host driver shall set
this register before issuing a command followed by a data transfer, or before issuing a
resume command. To prevent data loss, the SDHC prevents writing to the bits, that are
involved in the data transfer of this register, when data transfer is active. These bits are
DPSEL, MBSEL, DTDSEL, AC12EN, BCEN and DMAEN.
The host driver shall check the PRSSTAT[CDIHB] and the PRSSTAT[CIHB] before
writing to this register. When the PRSSTAT[CDIHB] is set, any attempt to send a
command with data by writing to this register is ignored; when the PRSSTAT[CIHB] bit
is set, any write to this register is ignored.
On sending commands with data transfer invovled, it is mandatory that the block size is
non-zero. Besides, block count must also be non-zero, or indicated as single block
transfer (bit 5 of this register is ‘0’ when written), or block count is disabled (bit 1 of this
register is ‘0’ when written), otherwise SDHC will ignore the sending of this command
and do nothing. For write command, with all above restrictions, it is also mandatory that
the write protect switch is not active (WPSPL bit of Present State Register is ‘1),
otherwise SDHC will also ignore the command.
If the commands with data transfer does not receive the response in 64 clock cycles, i.e.,
response time-out, SDHC will regard the external device does not accept the command
and abort the data transfer. In this scenario, the driver should issue the command again to
re-try the transfer. It is also possible that for some reason the card responds the command
but SDHC does not receive the response, and if it is internal DMA (either simple DMA
or ADMA) read operation, the external system memory is over-written by the internal
DMA with data sent back from the card.
The following table shows the summary of how register settings determine the type of
data transfer.
1250
Multi/Single block select
CMDARG
31–0
Field
Table 45-7. Transfer Type Register Setting for Various Transfer Types
0
Command Argument
The SD/MMC command argument is specified as bits 39-8 of the command format in the SD or MMC
specification.This register is write protected when the PRSSTAT[CDIHB0] bit is set.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Block count enable
SDHC_CMDARG field descriptions
Don't care
Table continues on the next page...
Description
Block count
Don't care
Freescale Semiconductor, Inc.
Single transfer
Function