MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1018

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory Map/Register Definition
1. The number of the last remaining available mailboxes is defined by the least value between the parameter
2. If Rx Individual Mask Registers are not enabled then all Rx FIFO filters are affected by the Rx FIFO Global Mask.
1018
NUMBER_OF_MB minus 1 and the MCR[MAXMB] field.
Reserved
EACEN
MRP
15–0
Field
RRS
18
17
16
See Section "Arbitration process" and Section "Protocol Timing" for more details.
NOTE: The recommended value for TASD is 22.
Mailboxes Reception Priority
If this bit is set the matching process starts from the Mailboxes and if no match occurs the matching
continues on the Rx FIFO. This bit can only be written in Freeze mode as it is blocked by hardware in
other modes.
0
1
Remote Request Storing
If this bit is asserted Remote Request Frame is submitted to a matching process and stored in the
corresponding Message Buffer in the same fashion of a Data Frame. No automatic Remote Response
Frame will be generated.
If this bit is negated the Remote Request Frame is submitted to a matching process and an automatic
Remote Response Frame is generated if a Message Buffer with CODE=0b1010 is found with the same
ID.
This bit can only be written in Freeze mode as it is blocked by hardware in other modes.
0
1
Entire Frame Arbitration Field Comparison Enable for Rx Mailboxes
This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes filters with their corresponding
bits in the incoming frame by the matching process. This bit does not affect matching for Rx FIFO. This bit
can only be written in Freeze mode as it is blocked by hardware in other modes.
0
1
This read-only field is reserved and always has the value zero.
• PSEG2 is the value in CTRL1[PSEG2] field;
• PROPSEG is the value in CTRL1[PROPSEG] field;
• PRESDIV is the value in CTRL1[PRESDIV] field.
Matching starts from Rx FIFO and continues on Mailboxes.
Matching starts from Mailboxes and continues on Rx FIFO.
Remote Response Frame is generated.
Remote Request Frame is stored.
Rx Mailbox filter’s IDE bit is always compared and RTR is never compared despite mask bits.
Enables the comparison of both Rx Mailbox filter’s IDE and RTR bit with their corresponding bits
within the incoming frame. Mask bits do apply.
CANx_CTRL2 field descriptions (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Description
Freescale Semiconductor, Inc.