MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1536

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional description
50.4.4.1 IDCODE instruction
IDCODE selects the 32-bit device identification register as the shift path between TDI
and TDO. This instruction allows interrogation of the MCU to determine its version
number and other part identification data. IDCODE is the instruction placed into the
instruction register when the JTAGC block is reset.
50.4.4.2 EZPORT instruction
The EZPORT instruction allows for the EZPORT module to program the on-chip flash
from a simple 4-pin interface. The JTAGC forces the core into a reset state and forces the
EZPORT mode select/chip select low. In this mode, the flash can be programmed
through the JTAG test port pins, which are connected to the EZPORT module.
50.4.4.3 SAMPLE/PRELOAD instruction
The SAMPLE/PRELOAD instruction has two functions:
1536
ARM JTAG-DP Reserved
CLAMP
ARM JTAG-DP Reserved
BYPASS
Instruction
• The SAMPLE portion of the instruction obtains a sample of the system data and
• The PRELOAD portion of the instruction initializes the boundary scan register cells
control signals present at the MCU input pins and just before the boundary scan
register cells at the output pins. This sampling occurs on the rising edge of TCK in
the Capture-DR state when the SAMPLE/PRELOAD instruction is active. The
sampled data is viewed by shifting it through the boundary scan register to the TDO
output during the Shift-DR state. Both the data capture and the shift operation are
transparent to system operation.
before selecting the EXTEST or CLAMP instructions to perform boundary scan
tests. This is achieved by shifting in initialization data to the boundary scan register
during the Shift-DR state. The initialization data is transferred to the parallel outputs
Table 50-3. 4-bit JTAG instructions (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Code[3:0]
1011
1100
1110
1111
This instruction goes the ARM JTAG-DP controller. See the
ARM JTAG-DP documentation for more information.
Selects bypass register while applying preloaded values to
output pins and asserting functional reset
This instruction goes the ARM JTAG-DP controller. See the
ARM JTAG-DP documentation for more information.
Selects bypass register for data operations
Instruction Summary
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