MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1392

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional description
46.4.1 Detailed operating mode descriptions
The following sections provide detailed descriptions of the above modes.
46.4.1.1 Normal mode
Normal mode is the simplest mode of the I
A time slot is a unit of data and the RCCR[WL] bits define the number of bits in a time
slot. In continuous clock mode, a frame sync occurs at the beginning of each frame. The
following factors determine the length of the frame:
If normal mode is configured with more than one time slot per frame, data transfers only
in the first time slot of the frame. No data transfers in subsequent time slots. In normal
mode, TCCR[DC] values corresponding to more than a single time slot in a frame only
result in lengthening the frame.
46.4.1.1.1 Normal mode transmit
Conditions for data transmission from the I
When the above conditions occur in normal mode, the next data word transfers into the
transmit shift register (TXSR) from the transmit data register 0 (TX0), or from the
transmit FIFO 0 register, if enabled.
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1. I
2. Enable FIFO and configure transmit and receive watermark if the FIFO is used
3. Write data to transmit data register (TX)
4. Transmitter enabled (CR[TE] = 1)
5. Frame sync active (for continuous clock case)
6. Bit clock begins (for gated clock case)
• Period of the serial bit clock (TCCR[DIV2], TCCR[PSR], TCCR[PM] bits for
• Number of bits per time slot (RCCR[WL] bits)
• Number of time slots per frame (TCCR[DC] bits)
• In continuous clock mode, the data word is transmitted on arrival of frame-sync
internal clock or the frequency of the external clock on the STCK port)
preceded by clocks.
2
S enabled (CR[I2SEN] = 1)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
2
2
S. It transfers data in one time slot per frame.
S in normal mode are:
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