MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 879

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

The SWOCTRL register can be updated at each rising edge of system clock (SWOC = 0)
or by the enhanced PWM synchronization (SWOC = 1 and SYNCMODE = 1) according
to the following flowchart.
In the case of enhanced PWM synchronization, the SWOCTRL register synchronization
depends on SWSOC and HWSOC bits.
Freescale Semiconductor, Inc.
each rising edge of system clock
update SWOCTRL register at
no =
with its buffer value
update SWOCTRL
Figure 36-219. SWOCTRL Register Synchronization Flowchart
rising edge
of system
clock ?
end
= yes
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
0 =
with its buffer value
update SWOCTRL
SWOCTRL is updated
by software trigger
SWSYNC
bit ?
end
= 1
1 =
software
trigger
SWSOC
0 =
bit ?
SWOC
begin
bit ?
= 0
end
= 1
end
update SWOCTRL register by
1 =
0 =
enhanced PWM synchronization
PWM synchronization
SYNCMODE
HWSOC
bit ?
bit ?
hardware
wait hardware trigger n
trigger
with its buffer value
SWOCTRL is updated
update SWOCTRL
by hardware trigger
HWTRIGMODE
clear TRIGn bit
Chapter 36 FlexTimer (FTM)
= 1
= 0
TRIGn
bit ?
bit ?
end
= 1
= 0
end
= 0
= 1
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