MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 183

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

1. Resumes normal run mode operation by executing the LLWU interrupt service routine.
2. Follows the reset flow with the LLWU interrupt flag set for the NVIC.
7.3 Entering and exiting power modes
The WFI instruction invokes wait and stop modes for the chip. The processor exits the
low-power mode via an interrupt. The
describes interrupt operation and what peripherals can cause interrupts.
Recovery from VLLSx is through the wake-up Reset event. The chip wake-ups from
VLLSx by means of reset, an enabled pin or enabled module. See the table "LLWU
inputs" in the LLWU configuration section for a list of the sources.
The wake-up flow from VLLSx is through reset. The wakeup bit in the SRS registers in
the Mode Controller is set indicating that the chip is recovering from a low power mode.
Code execution begins; however, the I/O pins are held in their pre low power mode entry
states, and the system oscillator and MCG registers are reset (even if EREFSTEN had
been set before entering VLLSx). Software must clear this hold by writing a 1 to the
ACKISO bit in the Control and Status register in the LLWU module.
If the oscillator was configured to continue running during VLLSx modes, it must be re-
configured before the ACKISO bit is cleared. The oscillator configuration within the
MCG is cleared after VLLSx recovery and the oscillator will stop when ACKISO is
cleared unless the register is re-configured.
Freescale Semiconductor, Inc.
BAT (backup
battery only)
Chip mode
The WFE instruction can have the side effect of entering a low-
power mode, but that is not its intended usage. See ARM
documentation for more on the WFE instruction.
To avoid unwanted transitions on the pins, software must re-
initialize the I/O pins to their pre-low-power mode entry states
before releasing the hold.
The chip is powered down except for the VBAT supply. The RTC and
the 32-byte VBAT register file for customer-critical data remain
powered.
Description
Table 7-1. Chip power modes (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Nested Vectored Interrupt Controller (NVIC)
NOTE
NOTE
Core mode
Chapter 7 Power Management
Off
Sequence
Power-up
recovery
method
Normal
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