MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1262

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory map and register definition
45.4.11 Protocol Control Register (SDHC_PROCTL)
There are three cases to restart the transfer after stop at the block gap. Which case is
appropriate depends on whether the SDHC issues a suspend command or the SD card
accepts the suspend command.
Any time stop at block gap request stops the data transfer, the host driver shall wait for a
transfer complete (in the interrupt status register), before attempting to restart the transfer.
When restarting the data transfer by continue request, the host driver shall clear the stop
at block gap request before or simultaneously.
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1. If the host driver does not issue a suspend command, the continue request shall be
2. If the host driver issues a suspend command and the SD card accepts it, a resume
3. If the host driver issues a suspend command and the SD card does not accept it, the
used to restart the transfer.
command shall be used to restart the transfer.
continue request shall be used to restart the transfer.
CIHB
Field
0
This status bit is generated if either the DLA or the RTA is set to 1. If this bit is 0, it indicates that the
SDHC can issue the next SD/MMC Command. Commands with a busy signal belong to CDIHB (e.g. R1b,
R5b type). Except in the case when the command busy is finished, changing from 1 to 0 generates a
transfer complete interrupt in the interrupt status register.
NOTE: The SD host driver can save registers for a suspend transaction after this bit has changed from 1
0b
1b
Command Inhibit (CMD)
If this status bit is 0, it indicates that the CMD line is not in use and the SDHC can issue a SD/MMC
Command using the CMD line.
This bit is set also immediately after the transfer type register is written. This bit is cleared when the
command response is received. Even if the CDIHB bit is set to 1, Commands using only the CMD line can
be issued if this bit is 0. Changing from 1 to 0 generates a command complete interrupt in the interrupt
status register. If the SDHC cannot issue the command because of a command conflict error (Refer to
command CRC error) or because of a command not issued by auto CMD12 error, this bit will remain 1
and the command complete is not set. The status of issuing an auto CMD12 does not show on this bit.
0b
1b
Can issue command which uses the DAT line
Cannot issue command which uses the DAT line
Can issue command using only CMD line
Cannot issue command
to 0.
SDHC_PRSSTAT field descriptions (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Description
Freescale Semiconductor, Inc.