MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1260

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory map and register definition
1260
PEROFF
HCKOFF
IPGOFF
SDOFF
Field
7
6
5
4
During a write transaction, a block gap event interrupt is generated when this bit is changed to 0, as result
of the stop at block gap request being set. This status is useful for the host driver in determining when to
issue commands during write busy state.
0b
1b
SD Clock Gated Off Internally
This status bit indicates that the SD clock is internally gated off, because of buffer over/under-run or read
pause without read wait assertion, or the driver has cleared SYSCTL[SDCLKEN] bit to stop the SD clock.
This bit is for the host driver to debug data transaction on the SD bus.
0b
1b
SDHC clock
Gated Off Internally
This status bit indicates that the SDHC clock is internally gated off. This bit is for the host driver to debug
transaction on the SD bus. When INITA bit is set, SDHC sending 80 clock cycles to the card, the
SDCLKEN bit must be ‘1’ to enable the output card clock, otherwise the
SDHC clock
will never be gate off, so
SDHC clock
and
bus clock
will be always active.
0b
1b
System Clock
Gated Off Internally
This status bit indicates that the system clock is internally gated off. This bit is for the host driver to debug
during a data transfer.
0b
1b
Bus Clock
Gated Off Internally
This status bit indicates that the bus clock is internally gated off. This bit is for the host driver to debug.
No valid data
Transferring data
SD clock is active
SD clock is gated off
SDHC clock
is active
SDHC clock
is gated off
System clock
is active
System clock
is gated off
SDHC_PRSSTAT field descriptions (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table continues on the next page...
Description
Freescale Semiconductor, Inc.