MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 536

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Initialization / Application Information
1. FLL_R is the reference divider selected by the C1[FRDIV] bits, PLL_R is the reference divider selected by C5[PRDIV] bits,
This section will include 3 mode switching examples using an 4 MHz external crystal. If
using an external clock source less than 2 MHz, the MCG should not be configured for
any of the PLL modes (PEE and PBE).
24.5.3.1 Example 1: Moving from FEI to PEE Mode : External Crystal
In this example, the MCG will move through the proper operational modes from FEI to
PEE to achieve 48 MHz MCGOUTCLK frequency from 4 MHz external crystal
reference. First, the code sequence will be described. Then a flowchart will be included
which illustrates the sequence.
536
FEI (FLL engaged internal)
FEE (FLL engaged external)
FBE (FLL bypassed external)
FBI (FLL bypassed internal)
PEE (PLL engaged external)
PBE (PLL bypassed external)
BLPI (Bypassed low power internal)
BLPE (Bypassed low power external)
Clock Mode
1. First, FEI must transition to FBE mode:
F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32] bits, and M is the multiplier selected by C6[VDIV] bits.
b. C1 = 0x90
a. C2 = 0x1C
• C2[RANGE] set to 2'b01 because the frequency of 4 MHz is within the high
• C2[HGO] set to 1 to configure the crystal oscillator for high gain operation
• C2[EREFS] set to 1, because a crystal is being used
= 4 MHz, MCGOUTCLK Frequency = 48 MHz
frequency range
Table 24-15. MCGOUTCLK Frequency Calculation Options
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
(f
(f
f
f
(f
f
f
f
f
ext
int
ext
int
ext
MCGOUTCLK
int
ext
ext
* F)
/ FLL_R) *F
/ PLL_R) * M
1
Typical f
immediately after reset.
f
31.25 kHz to 39.0625 kHz
f
31.25 kHz to 39.0625 kHz
Typical f
f
2 – 4 MHz
f
2 – 4 MHz
Note
ext
ext
ext
ext
/ FLL_R must be in the range of
/ FLL_R must be in the range of
/ PLL_R must be in the range of
/ PLL_R must be in the range of
Freescale Semiconductor, Inc.
MCGOUTCLK
int
= 32 kHz
= 20 MHz