MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 55

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

2.3.2 System Modules
The following system modules are available on this device.
Freescale Semiconductor, Inc.
ARM Cortex-M4
NVIC
AWIC
Debug interfaces
System integration module (SIM)
Mode controller
Power management controller (PMC)
Low-leakage wakeup unit (LLWU)
Miscellaneous control module (MCM)
Module
Module
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
The ARM Cortex-M4 is the newest member of the Cortex M Series of processors
targeting microcontroller cores focused on very cost sensitive, deterministic,
interrupt driven environments. The Cortex M4 processor is based on the ARMv7
Architecture and Thumb®-2 ISA and is upward compatible with the Cortex M3,
Cortex M1, and Cortex M0 architectures. Cortex M4 improvements include an
ARMv7 Thumb-2 DSP (ported from the ARMv7-A/R profile architectures) providing
32-bit instructions with SIMD (single instruction multiple data) DSP style multiply-
accumulates and saturating arithmetic.
The ARMv7-M exception model and nested-vectored interrupt controller (NVIC)
implement a relocatable vector table supporting many external interrupts, a single
non-maskable interrupt (NMI), and priority levels.
The NVIC replaces shadow registers with equivalent system and simplified
programmability. The NVIC contains the address of the function to execute for a
particular handler. The address is fetched via the instruction port allowing parallel
register stacking and look-up. The first sixteen entries are allocated to ARM
internal sources with the others mapping to MCU-defined interrupts.
The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is
to detect asynchronous wake-up events in stop modes and signal to clock control
logic to resume system clocking. After clock restart, the NVIC observes the
pending interrupt and performs the normal interrupt or event processing.
Most of this device's debug is based on the ARM CoreSight
debug interfaces are supported:
The SIM includes integration logic and several module configuration settings.
The MC provides control and protection on entry and exit to each power mode,
control for the Power management controller (PMC), and reset entry and exit for
the complete MCU.
The PMC provides the user with multiple power options. Ten different modes are
supported that allow the user to optimize power consumption for the level of
functionality needed. Includes power-on-reset (POR) and integrated low voltage
detect (LVD) with reset (brownout) capability and selectable LVD trip points.
The LLWU module allows the device to wake from low leakage power modes (LLS
and VLLS) through various internal peripheral and external pin sources.
The MCM includes integration logic and embedded trace buffer details.
Table 2-3. System modules
Table 2-2. Core modules
Table continues on the next page...
• IEEE 1149.1 JTAG
• IEEE 1149.7 JTAG (cJTAG)
• Serial Wire Debug (SWD)
• ARM Real-Time Trace Interface
Description
Description
Chapter 2 Introduction
™
architecture. Four
55