MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 809

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

36.3.11 Synchronization (FTMx_SYNC)
This register configures the PWM synchronization.
A synchronization event can perform the synchronized update of MOD, CV, and
OUTMASK registers with the value of their write buffer and the FTM counter
initialization.
Freescale Semiconductor, Inc.
PWMSYNC
CAPTEST
FTMEN
WPDIS
Field
INIT
4
3
2
1
0
Capture Test Mode Enable
Enables the capture test mode.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0
1
PWM Synchronization Mode
Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization
Synchronization). The PWMSYNC bit configures the synchronization when SYNCMODE is zero.
0
1
Write Protection Disable
When write protection is enabled (WPDIS = 0), write protected bits can not be written. When write
protection is disabled (WPDIS = 1), write protected bits can be written. The WPDIS bit is the negation of
the WPEN bit. WPDIS is cleared when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1
and then 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
0
1
Initialize the Channels Output
When a 1 is written to INIT bit the channels output is initialized according to the state of their
corresponding bit in the OUTINIT register. Writing a 0 to INIT bit has no effect.
The INIT bit is always read as 0.
FTM Enable
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0
1
Capture test mode is disabled.
Capture test mode is enabled.
No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM
counter synchronization.
Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only
be used by OUTMASK and FTM counter synchronization.
Write protection is enabled.
Write protection is disabled.
Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not
use the FTM-specific registers.
All registers including the FTM-specific registers (second set of registers) are available for use with no
restrictions.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
FTMx_MODE field descriptions (continued)
Description
Chapter 36 FlexTimer (FTM)
(PWM
809