MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1416

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional description
46.4.6 Internal frame and clock shutdown
During transmit/receive operation, clearing TE/RE stops data transmission/reception
when the current frame ends. If the CR[TFRCLKDIS, RFRCLKDIS] bit is set in the
current or previous frames, the I
the current frame ends. After this, the TCRTFRC]] and TCR[RFRC] status bits are set to
indicate the frame completion state. If TE is cleared four clock cycles before the next
frame, an extra invalid frame is generated.
The following figure is an illustration of transmission case where:
If CR[TFRCLKDIS or RFRCLKDIS] bit is not set while CR[TE or RE] is cleared, the
I
setting CR[TFRCLKDIS or RFRCLKDIS], the I
of the current frame. Following this, the TFRC/RFRC status bits are set to indicate the
frame completion state.
1416
2
S continues generating frame sync and clock signals (if direction is from the I
• TCR[TXDIR] and TCR[TFDIR] are set
• CR[TE] is cleared
• CR[TFRCLKDIS] is set during the current or previous frame
Figure 46-59. CR[TFRCLKDIS] assertion in current or previous frame as CR[TE] is
Transmit data 0 (with exception status)
Transmit data 1 (without exception)
Transmit data 0 (without exception)
CR[TFRCLKDIS]
Table 46-55. I
Interrupt
ISR[TFRC]
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Tx data
CR[TE]
CLK
FS
2
Transmit data 1 interrupts (n = 1)
2
S stops driving the frame sync and clock signals when
S transmit data interrupts (continued)
Disabled
2
S stops driving these signals at the end
TIE
1
1
1
TUEn
Freescale Semiconductor, Inc.
0
1
0
TFEn/TDEn
2
S), Upun
1
1
1