MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1377

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
46.3.10 I
The I2S Transmit and Receive Control (TCCR and RCCR) registers are 19-bit, read/write
control registers used to direct the operation of the I2S. The Clock and Reset Module
(CRM) can source the I2S clock (network clock) from multiple sources and perform
fractional division to support commonly used audio bit rates. The CRM can maintain the
network clock frequency at a constant rate even in cases where the peripheral clock
frequency changes. These registers control the I2S clock generator, bit and frame sync
rates, word length, and number of words per frame for the serial data. The TCCR register
is dedicated to the transmit section, and the RCCR register is dedicated to the receive
section except in Synchronous mode, in which the TCCR register controls both the
receive and transmit sections. Power-on reset clears all TCCR and RCCR bits. I2S reset
does not affect the TCCR and RCCR bits. The control bits are described in the following
paragraphs. Although the bit patterns of the TCCR and RCCR registers are the same, the
contents of these two registers can be programmed differently.
Addresses: I2S0_TCCR is 4002_F000h base + 24h offset = 4002_F024h
Freescale Semiconductor, Inc.
Bit
W
R
Reserved
31
0
31–19
16–13
DIV2
Field
PSR
WL
18
17
30
0
29
0
28
0
2
S Transmit Clock Control Registers (I2Sx_TCCR)
This read-only field is reserved and always has the value zero.
Divide By 2.
This bit controls a divide-by-two divider in series with the rest of the prescalers.
0
1
Prescaler Range.
This bit controls a fixed divide-by-eight prescaler in series with the variable prescaler. It extends the range
of the prescaler for those cases where a slower bit clock is required.
0
1
Word Length Control.
Specifies the number of bits per data word being transferred by the I
Length Divider in the Clock Generator. They also control the frame sync pulse length when the FSL bit is
cleared. In I2S Master mode, the I
27
0
Divider bypassed.
Divider used to divide clock by 2.
Prescaler bypassed.
Prescaler used to divide clock by 8.
26
0
25
0
0
24
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
0
22
0
I2Sx_TCCR field descriptions
21
0
Table continues on the next page...
20
0
19
0
2
18
S works with a fixed word length of 32, and the WL bits are used to
1
17
0
16
0
15
0
Description
WL
14
0
13
0
12
0
Chapter 46 Integrated interchip sound (I2S)
11
0
DC
10
0
2
S. These bits control the Word
0
9
0
8
0
7
0
6
0
5
4
0
PM
0
3
0
2
0
1
1377
0
0