MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 108

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Analog
ADCx_SC2[REFSEL] bit selects the voltage reference sources for ADC. Refer to
REFSEL description in ADC chapter for more details.
The only reference option for the PGA is the 1.2 V VREF_OUT source. The VREF_OUT
signal can either be driven by an external voltage source via the VREF_OUT pin or from
the output of the VREF module. Ensure that the VREF module is disabled when an
external voltage source is used instead. For PGA maximum differential input signal
swing range, refer to the device data sheet for 16-bit ADC with PGA characteristics.
3.7.1.8 ADC triggers
The ADC supports both software and hardware triggers. The primary hardware
mechanism for triggering the ADC is the PDB. The PDB itself can be triggered by other
peripherals. For example: RTC (Alarm, Seconds) signal is connected to the PDB. The
PDB trigger can receive the RTC (alarm/seconds) trigger input forcing ADC conversions
in run mode (where PDB is enabled). On the other hand, the ADC can conduct
conversions in low power modes, not triggered by PDB. This allows the ADC to do
conversions in low power mode and store the output in the result register. The ADC
generates interrupt when the data is ready in the result register that wakes the system
from low power mode. The PDB can also be bypassed by using the ADCxTRGSEL bits
in the SOPT7 register.
For operation of triggers in different modes, refer to Power Management chapter.
3.7.1.9 Alternate clock
For this device, the alternate clock is connected to OSCERCLK.
3.7.1.10 ADC low-power modes
This table shows the ADC low-power modes and the corresponding chip low-power
modes.
108
• VREFH/VREFL - connected as the primary reference option
• 1.2 V VREF_OUT - connected as the V
This clock option is only usable when OSCERCLK is in the
MHz range. A system with OSCERCLK in the kHz range has
the optional clock source below minimum ADC clock operating
frequency.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
NOTE
ALT
reference option
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