MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1063

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

41.4.10 Interrupts
Each one of the message buffers can be an interrupt source, if its corresponding IMASK
bit is set. There is no distinction between Tx and Rx interrupts for a particular buffer,
under the assumption that the buffer is initialized for either transmission or reception.
Each of the buffers has assigned a flag bit in the IFLAG Registers. The bit is set when the
corresponding buffer completes a successful transmission/reception and is cleared when
the CPU writes it to '1' (unless another interrupt is generated at the same time).
If the Rx FIFO is enabled (bit RFEN on MCR set), the interrupts corresponding to MBs 0
to 7 have a different behavior. Bit 7 of the IFLAG1 becomes the "FIFO Overflow" flag;
bit 6 becomes the FIFO Warning flag, bit 5 becomes the "Frames Available in FIFO flag"
and bits 4-0 are unused. See the description of the Interrupt Flags 1 Register (IFLAG1)
for more information.
A combined interrupt for all MBs is generated by an Or of all the interrupt sources from
MBs. This interrupt gets generated when any of the MBs or FIFO generates an interrupt.
In this case the CPU must read the IFLAG Registers to determine which MB or FIFO
caused the interrupt.
The other interrupt sources (Bus Off, Error, Tx Warning, Rx Warning, and Wake Up)
generate interrupts like the MB ones, and can be read from both the Error and Status
Register 1 and 2. The Bus Off, Error, Tx Warning and Rx Warning interrupt mask bits
are located in the Control 1 Register; the Wake-Up interrupt mask bit is located in the
MCR.
41.4.11 Bus Interface
The CPU access to FlexCAN registers are subject to the following rules:
Freescale Semiconductor, Inc.
• Unrestricted read and write access to supervisor registers (registers identified with S/
• Read and write access to implemented reserved address space results in access error.
U in Table "Module Memory Map" in Supervisor Mode or with S only) results in
access error.
It must be guaranteed that the CPU only clears the bit causing
the current interrupt. For this reason, bit manipulation
instructions (BSET) must not be used to clear interrupt flags.
These instructions may cause accidental clearing of interrupt
flags which are set after entering the current interrupt service
routine.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Note
Chapter 41 CAN (FlexCAN)
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