MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1401

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

normal mode), the internal bit clock is enabled onto the appropriate clock port. This
allows data to be transferred out in periodic intervals in gated clock mode. With an
external clock, the I
begins, valid data is shifted in. Ensure all RCCR[DC] bits are cleared when the module is
used in gated mode. In gated mode the ISR[TFS], ISR[RFS], ISR[TLS], ISR[RLS],
ISR[TRFC] and ISR[RFRC] bits are not generated.
For gated clock operated in external clock mode, proper clock signalling must apply to
the I
must be set. When TCR[TSCKP] is set, CR[CLKIST] value must be cleared. If the I
uses rising edge transition to clock data (TCR[TSCKP] = 0) and the falling edge
transition to latch data (RCR[RSCKP] = 0), the clock must be in an active low state when
idle. If the I
edge transition to latch data (RCR[RSCKP] = 1), the clock must be in a active high state
when idle. The following diagrams illustrate the different edge clocking/latching.
Freescale Semiconductor, Inc.
Figure 46-52. External gated mode timing - rising edge clocking/falling edge latching
Figure 46-50. Internal gated mode timing - rising edge clocking/falling edge latching
Figure 46-51. Internal gated mode timing - falling edge clocking/rising edge latching
2
S STCK for it to function properly. When TCR[TSCKP] is cleared, CR[CLKIST]
STXD
STXD
STXD
STCK
STCK
STCK
SRXD
SRXD
TCR[TSCKP] = 0, RCR[RSCKP] = 0
SRXD
TCR[TSCKP] = 0, RCR[RSCKP] = 0
TCR[TSCKP] = 1, RCR[RSCKP] = 1
2
S uses falling edge transition to clock data (TCR[TSCKP] = 1) and the rising
2
S module waits for a clock signal to be received. After the clock
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Chapter 46 Integrated interchip sound (I2S)
2
S
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