MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 81

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

3.3.7.5 Write Access Restrictions for RGD0 Registers
In addition to configuring the initial state of RGD0, the MPU implements further access
control on writes to the RGD0 registers. Specifically, the MPU assigns a priority scheme
where the debugger is treated as the highest priority master followed by the core and then
all the remaining masters.
The MPU does not allow writes from the core to affect the RGD0 start or end addresses
nor the permissions associated with the debugger; it can only write the permission fields
associated with the other masters.
These protections (summarized below) guarantee that the debugger always has access to
the entire address space and those rights cannot be changed by the core or any other bus
master.
3.3.8 Peripheral Bridge Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Freescale Semiconductor, Inc.
RGD0_WORD0
RGD0_WORD1
RGD0_WORD2
RGD0_WORD3
RGDAAC0
Core
Debugger
All other masters
Bus Master
Register
Table 3-20. Reset Values for RGD0 Registers
Table 3-21. Write Access to RGD0 Registers
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
0000_0000h
FFFF_FFFFh
0061_F7DFh
0000_0001h
0061_F7DFh
Partial. The Core cannot write to the following registers or
register fields:
NOTE: Changes to the RGD0_WORD2 alterable fields
Yes
No
• RGD0_WORD0, RGD0_WORD1, RGD0_WORD3
• RGD0_WORD2[M1SM, M1UM]
• RGDAAC0[M1SM, M1UM]
should be done via a write to RGDAAC0.
Write Access?
Reset value
Chapter 3 Chip Configuration
81