MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 864

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MK30DN512ZVLK10

Manufacturer Part Number
MK30DN512ZVLK10
Description
ARM Microcontrollers - MCU KINETIS 512K SLCD
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK30DN512ZVLK10

Core
ARM Cortex M4
Processor Series
K30
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-80
Mounting Style
SMD/SMT

Available stocks

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Part Number:
MK30DN512ZVLK10
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Quantity:
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Functional Description
36.4.8.1 Asymmetrical PWM
In combine mode, the control of the PWM signal first edge (when the channel (n) match
occurs, that is, FTM counter = C(n)V) is independent of the control of the PWM signal
second edge (when the channel (n+1) match occurs, that is, FTM counter = C(n+1)V).
So, combine mode allows the generation of asymmetrical PWM signals.
36.4.9 Complementary Mode
The complementary mode is selected when (FTMEN = 1), (QUADEN = 0), (DECAPEN
= 0), (COMBINE = 1), (CPWMS = 0), and (COMP = 1).
In complementary mode the channel (n+1) output is the inverse of the channel (n) output.
If (FTMEN = 1), (QUADEN = 0), (DECAPEN = 0), (COMBINE = 1), (CPWMS = 0),
and (COMP = 0), then the channel (n+1) output is the same as the channel (n) output.
864
Figure 36-202. Channel (n) Output If (C(n+1)V > MOD) and (CNTIN < C(n)V = MOD)
channel (n) output
with ELSnB:ELSnA = X:1
channel (n) output
with ELSnB:ELSnA = 1:0
MOD = C(n)V
C(n+1)V
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
CNTIN
not fully 100% duty cycle
not fully 0% duty cycle
FTM counter
Freescale Semiconductor, Inc.

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