MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 460

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional description
21.4.4.1 Peak transfer rates
The peak transfer rates for several different source and destination transfers are shown in
the following tables. These tables assume:
This table presents a peak transfer rate comparison.
Internal-SRAM-to-internal-SRAM transfers occur at the core's datapath width. For all
transfers involving the internal peripheral bus, 32-bit transfer sizes are used. In all cases,
the transfer rate includes the time to read the source plus the time to write the destination.
21.4.4.2 Peak request rates
The second performance metric is a measure of the number of DMA requests that can be
serviced in a given amount of time. For this metric, assume that the peripheral request
causes the channel to move a single internal peripheral bus-mapped operand to/from
internal SRAM. The same timing assumptions used in the previous example apply to this
calculation. In particular, this metric also reflects the time required to activate the
channel.
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• Internal SRAM can be accessed with zero wait-states when viewed from the system
• All internal peripheral bus reads require two wait-states, and internal peripheral bus
• All internal peripheral bus accesses are 32-bits in size
address spaces remains important. However, the microarchitecture of the eDMA also
factors significantly into the resulting metric.
bus data phase
writes three wait-states, when viewed from the system bus data phase
100.0 MHz, 32b
133.3 MHz, 32b
150.0 MHz, 32b
System Speed,
66.7 MHz, 32b
83.3 MHz, 32b
Width
Table 21-292. eDMA peak transfer rates (Mbytes/sec)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Internal SRAM-to-
Internal SRAM
133.3
166.7
200.0
266.7
300.0
32b internal peripheral bus-
Internal SRAM
100.0
133.3
150.0
66.7
83.3
to-
Freescale Semiconductor, Inc.
32b internal peripheral bus
Internal SRAM-to-
106.7
120.0
53.3
66.7
80.0