MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1258

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory map and register definition
Address: SDHC_PRSSTAT is 400B_1000h base + 24h offset = 400B_1024h
1258
Reset
Reset
Bit
Bit
W
W
Reserved
R
R
31–24
22–17
DLSL
CLSL
CINS
Field
23
16
31
15
0
0
30
14
0
0
DAT Line Signal Level
This status is used to check the DAT line level to recover from errors, and for debugging.This is especially
useful in detecting the busy signal level from DAT[0]. The reset value is effected by the external pullup/
pulldown resistors. By default, the read value of this bit field after reset is 8’b11110111, when DAT[3] is
pulled down and the other lines are pulled up.
DAT[0] Data 0 line signal level
DAT[1] Data 1 line signal level
DAT[2] Data 2 line signal level
DAT[3] Data 3 line signal level
DAT[4] Data 4 line signal level
DAT[5] Data 5 line signal level
DAT[6] Data 6 line signal level
DAT[7] Data 7 line signal level
CMD Line Signal Level
This status is used to check the CMD line level to recover from errors, and for debugging. The reset value
is effected by the external pullup/pulldown resistor, by default, the read value of this bit after reset is 1b,
when the command line is pulled up.
This read-only field is reserved and always has the value zero.
Card Inserted
This bit indicates whether a card has been inserted. The SDHC debounces this signal so that the host
driver will not need to wait for it to stabilize. Changing from a 0 to 1 generates a card insertion interrupt in
the interrupt status register. Changing from a 1 to 0 generates a card removal interrupt in the interrupt
status register. A write to the force event register does not effect this bit.
0
29
13
0
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
28
12
0
0
DLSL
SDHC_PRSSTAT field descriptions
27
11
0
0
Table continues on the next page...
26
10
0
0
RTA
25
0
0
9
24
0
0
8
Description
CLSL
23
0
0
7
22
0
0
6
21
0
0
5
20
0
0
4
Freescale Semiconductor, Inc.
0
19
0
0
3
DLA
18
0
0
2
17
0
0
1
CINS
16
0
0
0