MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 355

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

18.3.3 Error Detail Register, Slave Port n (MPU_EDRn)
When the MPU detects an access error on slave port n, 32 bits of error detail are captured
in this read-only register and the corresponding bit in CESR[SPERR] is set. Information
on the faulting address is captured in the corresponding EARn register at the same time.
This register and the corresponding EARn register contain the most recent access error;
there are no hardware interlocks with CESR[SPERR] as the error registers are always
loaded upon the occurrence of each protection violation.
Addresses: MPU_EDR0 is 4000_D000h base + 14h offset = 4000_D014h
* Notes:
•
Freescale Semiconductor, Inc.
Reset
Reset
x = Undefined at reset.
Bit
Bit
W
W
Reserved
R
R
EATTR
31–16
EACD
15–8
EMN
Field
7–4
3–1
31
x*
15
x*
MPU_EDR1 is 4000_D000h base + 1Ch offset = 4000_D01Ch
MPU_EDR2 is 4000_D000h base + 24h offset = 4000_D024h
MPU_EDR3 is 4000_D000h base + 2Ch offset = 4000_D02Ch
MPU_EDR4 is 4000_D000h base + 34h offset = 4000_D034h
30
x*
14
x*
Error access control detail
Indicates the region descriptor with the access error.
If EDRn contains a captured error and EACD is cleared, an access did not hit in any region descriptor. If
only a single EACD bit is set, the protection error was caused by a single non-overlapping region
descriptor. If two or more EACD bits are set, the protection error was caused by an overlapping set of
region descriptors.
This read-only field is reserved and always has the value zero.
Error master number
Indicates the bus master that generated the access error.
Error attributes
Indicates attribute information about the faulting reference.
29
x*
13
x*
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
28
x*
12
x*
0
27
x*
11
x*
MPU_EDRn field descriptions
Table continues on the next page...
26
x*
10
x*
25
x*
x*
9
24
x*
x*
8
EACD
Description
23
x*
x*
7
22
x*
x*
6
EMN
Chapter 18 Memory Protection Unit (MPU)
21
x*
x*
5
20
x*
x*
4
19
x*
x*
3
EATTR
x*
x*
18
2
x*
x*
17
1
ERW
x*
x*
16
0
355