MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1362

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory map/register definition
1362
TFRCLKDIS
SYSCLKEN
I2SMODE
CLKIST
TCHEN
Field
6–5
10
9
8
7
This bit provides the option to keep the frame-sync and clock enabled or to disable them after the receive
frame in which the receiver is disabled. Writing to this bit has effect only when CR[RE] is disabled.The
receiver is disabled by clearing the CR[RE] bit.
0
1
Transmit Frame Clock Disable.
This bit provide option to keep the frame-sync and clock enabled or disabled after current transmit frame,
in which transmitter is disabled by clearing CR[TE] bit. Writing to this bit has effect only when I
enabled CR[TE] is disabled.
0
1
Clock Idle State.
This bit controls the idle state of the transmit clock port during I
idle state is `1' the clock polarity should always be negedge triggered and when clock idle = `0' the clock
polarity should always be positive edge triggered.
0
1
Two-Channel Operation Enable.
This bit allows I
data to RX0 and RX1 alternately and while transmitting, data is alternately transferred from TX0 and TX1
to TXSR. For an even number of slots, two-channel operation can be enabled to optimize usage of both
FIFOs or disabled as in the case of odd number of active slots. This feature is especially useful in I2S
mode, where data for left speaker can be placed in Tx-FIFO0 and for right speaker in Tx-FIFO1.
0
1
System Clock (Oversampling Clock) Enable.
When set, this bit allows the I
synchronous mode, and transmit internal clock mode are set. The relationship between bit clock and
network clock is determined by DIV2, PSR, and PM bits. This feature is especially useful in I2S master
mode to output oversampling clock on SRCK port.
0
1
I2S Mode Select
These bits allow the I
00
01
Continue frame-sync/clock generation after current frame during which CR[RE] is cleared. This may
be required when Frame-sync and Clocks are required from I
Stop frame-sync/clock generation at next frame boundary. This will be effective also in case where
receiver is already disabled in current or previous frames.
Continue frame-sync/clock generation after current frame during which CR[TE] is cleared. This may
be required when frame-sync and clocks are required from I
Stop frame-sync/clock generation at next frame boundary. This will be effective also in case where
transmitter is already disabled in current or previous frames.
Clock idle state is `0'.
Clock idle state is `1'.
Two-channel mode disabled.
Two-channel mode enabled.
Network clock not output on SRCK port.
Network clock output on SRCK port.
Normal mode
I
2
S master mode
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
2
I2Sx_CR field descriptions (continued)
S to operate in the two-channel mode.In this mode while receiving, the RXSR transfers
2
S to operate in normal, I
Table continues on the next page...
2
S to output the (network clock) at the SRCK port, provided that
2
Description
S master or I
2
S slave mode.
2
S internal gated mode. Note: When Clock
2
S, even when no data is to be received.
2
S, even when no data is to be received.
Freescale Semiconductor, Inc.
2
S is