R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 102

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 CPU
Rev. 3.00 Sep. 28, 2009 Page 70 of 1650
REJ09B0313-0300
Classification Types
System
control
Floating-point
instructions
14
19
Operation
Code
CLRT
CLRMAC
LDBANK
LDC
LDS
NOP
RESBANK Register restoration from register bank
RTE
SETT
SLEEP
STBANK
STC
STS
TRAPA
FABS
FADD
FCMP
FCNVDS
FCNVSD
FDIV
FLDI0
FLDI1
FLDS
FLOAT
FMAC
FMOV
FMUL
FNEG
Function
T bit clear
MAC register clear
Register restoration from specified register
bank entry
Load to control register
Load to system register
No operation
Return from exception handling
T bit set
Transition to power-down mode
Register save to specified register bank entry
Store control register data
Store system register data
Trap exception handling
Floating-point absolute value
Floating-point addition
Floating-point comparison
Conversion from double-precision to single-
precision
Conversion from single-precision to double -
precision
Floating-point division
Floating-point load immediate 0
Floating-point load immediate 1
Floating-point load into system register FPUL
Conversion from integer to floating-point
Floating-point multiply and accumulate
operation
Floating-point data transfer
Floating-point multiplication
Floating-point sign inversion
No. of
Instructions
36
48