R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 905

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Table 17.5 Time for Monitoring SCL
Note: pcyc = Pφ × cyc
17.7
17.7.1
The bit field ICCR1.CKS[3:0] should not be H'7 or H'F at the same time as NF2CYC.PRS = 1.
17.7.2
In multi-master operation, when the setting for IIC transfer rate (ICCR1.CKS[3:0]) makes this LSI
slower than the other masters, pulse cycles with an unexpected length will infrequently be output
on SCL.
Be sure to specify a transfer rate that is at least 1/1.8 of the fastest transfer rate among the other
masters.
17.7.3
Reading ICDRR around the falling edge of the 8th clock might fail to fetch the receive data.
In addition, when RCVD is set to 1 around the falling edge of the 8th clock and the receive buffer
is full, a stop condition may not be issued.
Use either 1 or 2 below as a measure against the situations above.
1. In master receive mode, read ICDRR before the rising edge of the 8th clock.
2. In master receive mode, set the RCVD bit to 1 so that transfer proceeds in byte units.
CKS3
0
1
Usage Notes
Note on the Setting of ICCR1.CKS[3:0]
Settings for Multi-Master Operation
Note on Master Receive Mode
CKS2
0
1
0
1
Time for Monitoring SCL
9 tpcyc
21 tpcyc
39 tpcyc
87 tpcyc
Rev. 3.00 Sep. 28, 2009 Page 873 of 1650
Section 17 I
2
C Bus Interface 3 (IIC3)
REJ09B0313-0300