R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1160

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 USB 2.0 Host/Function Module (USB)
23.3.12 Interrupt Enabled Register 1 (INTENB1)
INTENB1 is a register that specifies the masking of various interrupts and controls the BRDY
interrupt status clear timing.
This register is initialized by a power-on reset. By a software reset, bits other than BRDYM are
initialized.
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 1128 of 1650
REJ09B0313-0300
Bit
15
14
13
12
R/W:
Bit:
Bit Name
⎯
BCHGE
⎯
DTCHE
15
R
0
-
BCHGE
R/W
14
0
13
R
0
-
DTCHE
Initial
Value
0
0
0
0
R/W
12
0
11
R
0
-
R/W
R
R/W
R
R/W
10
R
0
-
R
9
0
-
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
USB Bus Change Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled
Reserved
This bit is always read as 0. The write value should
always be 0.
Disconnection Detection Interrupt Enable during Full-
Speed Operation
The disconnection detection using this bit is valid
only when the host controller function is selected and
full-speed operation is performed. During high-speed
operation, software should be used to detect
disconnection by detecting no response from a
function or by another appropriate method.
0: Interrupt output disabled
1: Interrupt output enabled
Note: When high-speed operation established
R
8
0
-
(RHST = 11) is determined after a reset
handshake, keep DTCHE cleared to 0 during
high-speed communication.
R
7
0
-
R
6
0
-
SIGNE SACKE
R/W
5
0
R/W
4
0
R
3
0
-
BRDYM
R/W
2
0
R
1
0
-
R
0
0
-