R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1080

IC SUPERH MPU ROMLESS 240QFP

R5S72030W200FP

Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheets

Specifications of R5S72030W200FP

Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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Section 21 D/A Converter (DAC)
21.3.2
DACR is an 8-bit readable/writable register that controls the operation of the D/A converter.
DACR is initialized to H'1F by a power-on reset or in module standby mode.
Rev. 3.00 Sep. 28, 2009 Page 1048 of 1650
REJ09B0313-0300
Bit
7
6
5
4 to 0
Bit Name
DAOE1
DAOE0
DAE
D/A Control Register (DACR)
Initial value:
Initial
Value
0
0
0
All 1
R/W:
Bit:
DAOE1 DAOE0
R/W
R/W
R/W
R/W
R/W
7
0
R/W
6
0
Description
D/A Output Enable 1
Controls D/A conversion and analog output for channel 1.
0: Analog output of channel 1 (DA1) is disabled
1: D/A conversion of channel 1 is enabled. Analog output
D/A Output Enable 0
Controls D/A conversion and analog output for channel 0.
0: Analog output of channel 0 (DA0) is disabled
1: D/A conversion of channel 0 is enabled. Analog output
D/A Enable
Used together with the DAOE0 and DAOE1 bits to control
D/A conversion. Output of conversion results is always
controlled by the DAOE0 and DAOE1 bits. For details,
see table 21.3.
0: D/A conversion for channels 0 and 1 is controlled
1: D/A conversion for channels 0 and 1 is controlled
Reserved
These bits are always read as 1 and cannot be modified.
of channel 1 (DA1) is enabled.
of channel 0 (DA0) is enabled.
independently
together
R/W
DAE
5
0
4
1
-
-
3
1
-
-
2
1
-
-
1
1
-
-
0
1
-
-

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