R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1280

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 24 LCD Controller (LCDC)
24.3.7
LDLAOR sets the address width of the Y-coordinates increment used for LCDC to read the image
recognized by the graphics driver. This register specifies how many bytes the address from which
data is to be read should be moved when the Y coordinates have been incremented by 1. This
register does not have to be equal to the horizontal width of the LCD panel. When the memory
address of a point (X, Y) in the two-dimensional image is calculated by Ax + By+ C, this register
becomes equal to B in this equation.
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 1248 of 1650
REJ09B0313-0300
Bit
15 to 10
9
8
7
6 to 0
R/W:
Bit:
LAO15 LAO14 LAO13 LAO12 LAO11 LAO10
LCDC Line Address Offset Register for Display Data Fetch (LDLAOR)
R/W
15
0
Bit Name
LAO15 to
LAO10
LAO9
LAO8
LAO7
LAO6 to
LAO0
R/W
14
0
R/W
13
0
Initial
Value
All 0
1
0
1
All 0
R/W
12
0
R/W
11
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
10
0
Description
Line Address Offset
The minimum alignment unit of LDLAOR is 16 bytes.
Because the LCDC handles these values as 16-byte
data, the values written to the lower four bits of the
register are always treated as 0. The lower four bits of
the register are always read as 0. The initial values (×
resolution = 640) will continuously and accurately place
the VGA (640 × 480 dots) display data without skipping
an address between lines. For details, see tables 24.4
and 24.5.
A binary exponential at least as large as the horizontal
width of the image is recommended for the LDLAOR
value, taking into consideration the software operation
speed. When the hardware rotation function is used,
the LDLAOR value should be a binary exponential (in
this example, 256) at least as large as the horizontal
width of the image (after rotation, it becomes 240 in a
240 × 320 panel) instead of the horizontal width of the
LCD panel (320 in a 320 × 240 panel).
LAO9
R/W
9
1
LAO8
R/W
8
0
LAO7
R/W
7
1
LAO6
R/W
6
0
LAO5
R/W
5
0
LAO4
R/W
4
0
LAO3
R/W
3
0
LAO2
R/W
2
0
LAO1
R/W
1
0
LAO0
R/W
0
0