R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 95

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

2.3.3
The instruction formats and the meaning of source and destination operands are described below.
The meaning of the operand depends on the instruction code. The symbols used are as follows:
• xxxx: Instruction code
• mmmm: Source register
• nnnn: Destination register
• iiii: Immediate data
• dddd: Displacement
Table 2.9
Instruction Formats
0 format
15
n format
15
xxxx
xxxx
nnnn
xxxx
Instruction Format
Instruction Formats
xxxx xxxx
xxxx
xxxx
0
0
Source
Operand
—
—
Control register or
system register
R0 (Register direct) nnnn: Register
Control register or
system register
mmmm: Register
direct
R15 (Register
indirect with post-
increment)
R0 (Register direct) nnnn: (Register
Destination
Operand
—
nnnn: Register
direct
nnnn: Register
direct
direct
nnnn: Register
indirect with pre-
decrement
R15 (Register
indirect with pre-
decrement)
nnnn: Register
direct
indirect with post-
increment)
Rev. 3.00 Sep. 28, 2009 Page 63 of 1650
Example
NOP
MOVT
STS
DIVU
STC.L SR,@-Rn
MOVMU.L
MOVMU.L
MOV.L R0,@Rn+
REJ09B0313-0300
Section 2 CPU
Rn
MACH,Rn
R0,Rn
Rm,@-R15
@R15+,Rn