R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1105

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
19
18
17
16
15 to 10
Bit Name
AC1CLR
AC0CLR
DREQ1EN 0
DREQ0EN 0
—
Initial
Value
0
0
All 0
R/W
R/W
R/W
R/W
R/W
R
Description
FLECFIFO Clear
Clears FLECFIFO. When changing the read/write
direction, clear the FIFO.
0: Retains the FLECFIFO value. In flash-memory
1: Clears FLECFIFO. After FLECFIFO has been
FLDTFIFO Clear
Clears FLDTFIFO. When changing the read/write
direction, clear the FIFO.
0: Retains the FLDTFIFO value. In flash-memory
1: Clears FLDTFIFO. After FLDTFIFO has been
FLECFIFODMA Request Enable
Enables or disables the DMA transfer request issued
from FLECFIFO.
0: Disables the DMA transfer request issued from
1: Enables the DMA transfer request issued from
FLDTFIFODMA Request Enable
Enables or disables the DMA transfer request issued
from FLDTFIFO.
0: Disables the DMA transfer request issued from the
1: Enables the DMA transfer request issued from the
Reserved
These bits are always read as 0. The write value should
always be 0.
access, this bit should be cleared to 0.
cleared, this bit should be cleared to 0.
access, this bit should be cleared to 0.
cleared, this bit should be cleared to 0.
FLECFIFO
FLECFIFO
FLDTFIFO
FLDTFIFO
Section 22 AND/NAND Flash Memory Controller (FLCTL)
Rev. 3.00 Sep. 28, 2009 Page 1073 of 1650
REJ09B0313-0300