R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1023
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
R5S72030W200FP
Manufacturer:
SAMSUNG
Quantity:
1 001
Company:
Part Number:
R5S72030W200FP
Manufacturer:
Renesas Electronics America
Quantity:
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Section 19 Controller Area Network (RCAN-TL1)
• Halt mode
When RCAN-TL1 is in Halt mode, it cannot take part to the CAN bus activity. Consequently the
user can modify all the requested registers without influencing existing traffic on the CAN Bus. It
is important for this that the user waits for the RCAN-TL1 to be in halt mode before to modify the
requested registers - note that the transition to Halt Mode is not always immediate (transition will
occurs when the CAN Bus is idle or in intermission). After RCAN-TL1 transit to Halt Mode,
GSR4 is set.
Once the configuration is completed the Halt request needs to be released. RCAN-TL1 will join
CAN Bus activity after the detection of 11 recessive bits on the CAN Bus.
• Sleep mode
When RCAN-TL1 is in sleep mode the clock for the main blocks of the IP is stopped in order to
reduce power consumption. Only the following user registers are clocked and can be accessed:
MCR, GSR, IRR and IMR. Interrupt related to transmission (TXACK and ABACK) and reception
(RXPR and RFPR) cannot be cleared when in sleep mode (as TXACK, ABACK, RXPR and
RFPR are not accessible) and must to be cleared beforehand.
Rev. 3.00 Sep. 28, 2009 Page 991 of 1650
REJ09B0313-0300
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