R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 923

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

18.3.3
SSITDR is a 32-bit register that stores data to be transmitted.
Data written to this register is transferred to the shift register upon transmission request. If the data
word length is less than 32 bits, the alignment is determined by the setting of the PDTA control bit
in SSICR. The data in the buffer can be accessed by reading this register.
Initial value:
Initial value:
18.3.4
SSIRDR is a 32-bit register that stores receive messages.
Data in this register is transferred from the shift register each time data word is received. If the
data word length is less than 32 bits, the alignment is determined by the setting of the PDTA
control bit in SSICR.
Initial value:
Initial value:
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
Transmit Data Register (SSITDR)
Receive Data Register (SSIRDR)
R/W
R/W
31
15
31
15
R
R
0
0
0
0
R/W
R/W
30
14
30
14
R
R
0
0
0
0
R/W
R/W
29
13
29
13
R
R
0
0
0
0
R/W
R/W
28
12
28
12
R
R
0
0
0
0
R/W
R/W
27
11
27
11
R
R
0
0
0
0
R/W
R/W
26
10
26
10
R
R
0
0
0
0
R/W
R/W
25
25
R
R
0
9
0
0
9
0
R/W
R/W
24
24
R
R
0
8
0
0
8
0
R/W
R/W
23
23
R
R
0
7
0
0
7
0
Rev. 3.00 Sep. 28, 2009 Page 891 of 1650
R/W
R/W
22
22
R
R
0
6
0
0
6
0
Section 18 Serial Sound Interface (SSI)
R/W
R/W
21
21
R
R
0
5
0
0
5
0
R/W
R/W
20
20
R
R
0
4
0
0
4
0
R/W
R/W
19
19
R
R
0
3
0
0
3
0
REJ09B0313-0300
R/W
R/W
18
18
R
R
0
2
0
0
2
0
R/W
R/W
17
17
R
R
0
1
0
0
1
0
R/W
R/W
16
16
R
R
0
0
0
0
0
0