R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 943

IC SUPERH MPU ROMLESS 240QFP

R5S72030W200FP

Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheets

Specifications of R5S72030W200FP

Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S72030W200FP
Manufacturer:
SAMSUNG
Quantity:
1 001
Part Number:
R5S72030W200FP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5S72030W200FP
Manufacturer:
RENESAS
Quantity:
8 000
Section 18 Serial Sound Interface (SSI)
18.4.7
Serial Bit Clock Control
This function is used to control and select which clock is used for the serial bus interface.
If the serial clock direction is set to input (SCKD = 0), the SSI module is in clock slave mode and
the shift register uses the bit clock that was input to the SSISCK pin.
If the serial clock direction is set to output (SCKD = 1), the SSI module is in clock master mode,
and the shift register uses the oversampling clock, or the bit clock that is generated by dividing it.
The oversampling clock is then divided by the ratio in the serial oversampling clock divide ratio
bit (CKDV) in SSICR and used as the bit clock in the shift register.
In either case the module pin, SSISCK, is the same as the bit clock.
Rev. 3.00 Sep. 28, 2009 Page 911 of 1650
REJ09B0313-0300

Related parts for R5S72030W200FP