R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 942

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 18 Serial Sound Interface (SSI)
When an underflow or overflow error condition has matched, the CHNO [1:0] bit and the SWNO
bit can be used to recover the SSI module to a known status. When an underflow or overflow
occurs, the host can read the channel number and system word number to determine what point the
serial audio stream has reached. In the transmitter case, the host can skip forward through the data
it wants to transmit until it finds the sample data that matches what the SSI module is expecting to
transmit next, and so resynchronize with the audio data stream. In the receiver case the host CPU
can store null data to make the number of receive data items consistent until it is ready to store the
sample data that the SSI module is indicating will be received next, and so resynchronize with the
audio data stream.
18.4.6
The following procedures can be used for implementation.
(1)
1. Set SSICR.DMEN = 0 (disabling a DMA request) to stop the DMA transfer.
2. Wait for SSISR.DIRQ = 1 (transmit mode: the transmit buffer is empty) using a polling,
3. With SSICR.EN = 0 (disabling an SSI module operation), stop the transfer.
4. Before attempting another transfer, make sure that SSISR.IDST = 1 is reached.
5. Set SSICR.EN = 1 (enabling an SSI module operation).
6. Wait for SSISR.DIRQ = 1, using a polling, interrupt, or the like.
7. Setting SSICR.DMEN = 1 (enabling a DMA request) will restart the DMA transfer.
(2)
1. Set SSICR.DMEN = 0 (disabling a DMA request) to stop the DMA transfer.
2. Wait for SSISR.DIRQ = 1 (transmit mode: the transmit buffer is empty), using a polling,
3. With SSICR.EN = 0 (disabling an SSI module operation), stop the transfer.
4. Stop the DMAC with CHCR of the DMAC.
5. Before attempting another transfer, make sure that SSISR.IDST = 1 is reached.
6. Set SSICR.EN = 1 (enabling an SSI module operation).
7. Set the DMAC registers and start the transfer.
8. Setting SSICR.DMEN = 1 (enabling a DMA request) will restart the DMA transfer.
Rev. 3.00 Sep. 28, 2009 Page 910 of 1650
REJ09B0313-0300
interrupt, or the like.
interrupt, or the like.
Procedure for the transfer and stop without having to reconfigure the DMAC
Procedure for Reconfiguring the DMAC after an SSI stop
Temporary Stop and Restart Procedures in Transmit Mode