R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 17

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) ...................................449
11.1 Features ............................................................................................................................ 449
11.2 Input/Output Pins ............................................................................................................... 454
11.3 Register Descriptions ......................................................................................................... 455
10.5.1
10.5.2
10.5.3
10.5.4
10.5.5
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.3.7
11.3.8
11.3.9
11.3.10 Timer A/D Converter Start Request Cycle Set Buffer Registers
11.3.11 Timer Counter (TCNT)....................................................................................... 498
11.3.12 Timer General Register (TGR) ........................................................................... 498
11.3.13 Timer Start Register (TSTR) .............................................................................. 499
11.3.14 Timer Synchronous Register (TSYR)................................................................. 500
11.3.15 Timer Read/Write Enable Register (TRWER) ................................................... 502
11.3.16 Timer Output Master Enable Register (TOER) .................................................. 503
11.3.17 Timer Output Control Register 1 (TOCR1) ........................................................ 504
11.3.18 Timer Output Control Register 2 (TOCR2) ........................................................ 507
11.3.19 Timer Output Level Buffer Register (TOLBR) .................................................. 510
11.3.20 Timer Gate Control Register (TGCR) ................................................................ 511
11.3.21 Timer Subcounter (TCNTS) ............................................................................... 513
11.3.22 Timer Dead Time Data Register (TDDR)........................................................... 514
11.3.23 Timer Cycle Data Register (TCDR) ................................................................... 514
11.3.24 Timer Cycle Buffer Register (TCBR)................................................................. 515
11.3.25 Timer Interrupt Skipping Set Register (TITCR) ................................................. 515
11.3.26 Timer Interrupt Skipping Counter (TITCNT)..................................................... 517
11.3.27 Timer Buffer Transfer Set Register (TBTER) .................................................... 518
Setting of the Half-End Flag and Generation of the Half-End Interrupt............. 444
Timing of DACK and TEND Outputs ................................................................ 444
Notice about using external request mode .......................................................... 445
Notice about using on-chip peripheral module request mode or
auto-request mode............................................................................................... 446
Notes on Using Flag Bits .................................................................................... 447
Timer Control Register (TCR)............................................................................ 459
Timer Mode Register (TMDR) ........................................................................... 463
Timer I/O Control Register (TIOR) .................................................................... 466
Timer Interrupt Enable Register (TIER) ............................................................. 484
Timer Status Register (TSR)............................................................................... 487
Timer Buffer Operation Transfer Mode Register (TBTM)................................. 492
Timer Input Capture Control Register (TICCR) ................................................. 493
Timer A/D Converter Start Request Control Register (TADCR) ....................... 494
Timer A/D Converter Start Request Cycle Set Registers
(TADCORA_4 and TADCORB_4).................................................................... 497
(TADCOBRA_4 and TADCOBRB_4)............................................................... 497
Rev. 3.00 Sep. 28, 2009 Page xv of xxx
REJ09B0313-0300