R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 120

IC SUPERH MPU ROMLESS 240QFP

R5S72030W200FP

Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheets

Specifications of R5S72030W200FP

Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
R5S72030W200FP
Manufacturer:
SAMSUNG
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Part Number:
R5S72030W200FP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5S72030W200FP
Manufacturer:
RENESAS
Quantity:
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Section 2 CPU
2.4.10
Table 2.19 Bit Manipulation Instructions
Rev. 3.00 Sep. 28, 2009 Page 88 of 1650
REJ09B0313-0300
Instruction
BAND.B
BANDNOT.B #imm3,@(disp12,Rn)
BCLR.B
BCLR
BLD.B
BLD
BLDNOT.B
BOR.B
BORNOT.B
BSET.B
BSET
BST.B
BST
Bit Manipulation Instructions
#imm3,@(disp12,Rn)
#imm3,@(disp12,Rn)
#imm3,Rn
#imm3,@(disp12,Rn)
#imm3,Rn
#imm3,@(disp12,Rn)
#imm3,@(disp12,Rn)
#imm3,@(disp12,Rn)
#imm3,@(disp12,Rn)
#imm3,Rn
#imm3,@(disp12,Rn)
#imm3,Rn
Instruction Code
0011nnnn0iii1001
0100dddddddddddd
0011nnnn0iii1001
1100dddddddddddd
0011nnnn0iii1001
0000dddddddddddd
10000110nnnn0iii 0 → imm of Rn
0011nnnn0iii1001
0011dddddddddddd
10000111nnnn1iii imm of Rn → T
0011nnnn0iii1001
1011dddddddddddd
0011nnnn0iii1001
0101dddddddddddd
0011nnnn0iii1001
1101dddddddddddd
0011nnnn0iii1001
0001dddddddddddd
10000110nnnn1iii 1 → imm of Rn
0011nnnn0iii1001
0010dddddddddddd
10000111nnnn0iii T → imm of Rn
~(imm of (disp + Rn)) & T → T 3
0 → (imm of (disp + Rn))
(imm of (disp + Rn)) →
~(imm of (disp + Rn))
( imm of (disp + Rn)) | T → T
~( imm of (disp + Rn)) | T → T 3
1 → ( imm of (disp + Rn))
T → (imm of (disp + Rn))
Operation
(imm of (disp + Rn)) & T →
→ T
Execu-
tion
Cycles T Bit
3
3
3
1
3
3
1
1
3
3
1
Ope-
ration
result
Ope-
ration
result
Ope-
ration
result
Ope-
ration
result
Ope-
ration
result
Ope-
ration
result
Ope-
ration
result
SH2,
SH2E SH4 SH-2A
Compatibility
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

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