R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 139

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

The clock pulse generator blocks function as follows:
(1)
The crystal oscillator is used in which the crystal resonator is connected to the XTAL/EXTAL pin
or USB_X1/USB_X2 pin. One of them is selected according to the clock operating mode.
(2)
Divider 1 divides the output from the crystal oscillator or the external clock input. The division
ratio depends on the clock operating mode.
(3)
PLL circuit multiplies the frequency of the output from the divider 1. The multiplication ratio is
set by the frequency control register.
(4)
Divider 2 generates a clock signal whose operating frequency can be used for the internal clock,
the peripheral clock, and the bus clock. The division ratio of the internal clock and peripheral
clock are set by the frequency control register. The division ratio of the bus clock is determined by
the clock operating mode and the PLL multiplication ratio.
(5)
The clock frequency control circuit controls the clock frequency using the MD_CLK0 and
MD_CLK1 pins and the frequency control register (FRQCR).
(6)
The standby control circuit controls the states of the clock pulse generator and other modules
during clock switching, or sleep, software standby or deep standby mode.
In addition, the standby control register is provided to control the power-down mode of other
modules. For details on the standby control register, see section 28, Power-Down Modes.
(7)
The frequency control register (FRQCR) has control bits assigned for the following functions:
clock output/non-output from the CKIO pin during software standby mode, the frequency
multiplication ratio of PLL circuit, and the frequency division ratio of the internal clock and the
peripheral clock (Pφ).
Crystal Oscillator
Divider 1
PLL Circuit
Divider 2
Clock Frequency Control Circuit
Standby Control Circuit
Frequency Control Register (FRQCR)
Rev. 3.00 Sep. 28, 2009 Page 107 of 1650
Section 4 Clock Pulse Generator (CPG)
REJ09B0313-0300