R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 458

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 Direct Memory Access Controller (DMAC)
Rev. 3.00 Sep. 28, 2009 Page 426 of 1650
REJ09B0313-0300
CHCR
RS[3:0] MID
1000
010100
010101
011000
011001
011010 01
011011
100000 01
100001
100010 01
DMARS
RID
01
10
01
10
01
10
01
10
10
01
10
10
01
10
10
DMA Transfer
Request
Source
SSU_0
transmission
SSU_0
reception
SSU_1
transmission
SSU_1
reception
IIC3_0
transmission
IIC3_0
reception
IIC3_1
transmission
IIC3_1
reception
IIC3_2
transmission
IIC3_2
reception
IIC3_3
transmission
IIC3_3
reception
SCIF_0
transmission
SCIF_0
reception
SCIF_1
transmission
SCIF_1
reception
SCIF_2
transmission
SCIF_2
reception
DMA Transfer Request Signal
SSTXI0 (transmission empty or
transmission end)
SSTXI0 (reception full)
SSTXI1 (transmission empty or
transmission end)
SSTXI1 (reception full)
TXI0 (transmission data empty)
RXI0 (reception data full)
TXI1 (transmission data empty)
RXI1 (reception data full)
TXI2 (transmission data empty)
RXI2 (reception data full)
TXI3 (transmission data empty)
RXI3 (reception data full)
TXI0 (transmission FIFO data
empty)
RXI0 (reception FIFO data full)
TXI1 (transmit FIFO data empty) Any
RXI1 (reception FIFO data full)
TXI2 (transmission FIFO data
empty)
RXI2 (reception FIFO data full)
Transfer
Source
Any
SSRDR0 to
SSRDR3
Any
SSRDR0 to
SSRDR3
Any
ICDRR0
Any
ICDRR1
Any
ICDRR2
Any
ICDRR3
Any
SCFRDR_0 Any
SCFRDR_1 Any
Any
SCFRDR_2 Any
Transfer
Destination
SSTDR0 to
SSTDR3
Any
SSTDR0 to
SSTDR3
Any
ICDRT0
Any
ICDRT1
Any
ICDRT2
Any
ICDRT3
Any
SCFTDR_0
SCFTDR_1
SCFTDR_2
Bus
Mode
Cycle
steal