R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 850

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 16 Synchronous Serial Communication Unit (SSU)
Rev. 3.00 Sep. 28, 2009 Page 818 of 1650
REJ09B0313-0300
User operation
User operation
User operation
LSI operation
LSI operation
LSI operation
(MSB first)
(MSB first)
(1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0
(2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0
(3) When 32-bit data length is selected (SSRDR0 to SSRDR3 are valid) with CPOS = 0 and CPHS = 0
(LSB first)
(LSB first)
SSCK
RDRF
SSCK
RDRF
SSCK
RDRF
SCS
SCS
SCS
SSI
SSI
SSI
SSI
SSI
Figure 16.7 Example of Reception Operation (SSU Mode)
Dummy-read SSRDR0
Dummy-read SSRDR0
Dummy-read SSRDR0
Bit
Bit
Bit
Bit
Bit
0
7
0
7
0
SSRDR3
SSRDR0
Bit
SSRDR0 (LSB first transmission)
Bit
Bit
to
to
1
1
6
Bit
Bit
Bit
Bit
Bit
2
2
5
7
0
SSRDR1
SSRDR0
1 frame
Bit
Bit
Bit
Bit
Bit
3
0
7
3
4
SSRDR2
SSRDR1
Bit
Bit
Bit
to
to
4
4
3
1 frame
SSRXI interrupt
Bit
Bit
Bit
Bit
Bit
5
5
0
2
7
generated
Bit
Bit
Bit
Bit
Bit
6
6
1
0
7
SSRDR1
SSRDR2
1 frame
Bit
Bit
Bit
to
to
7
7
0
Bit
Bit
Bit
Bit
7
7
0
Read SSRDR0
0
Bit
Bit
Bit
Bit
6
0
7
1
SSRDR0
SSRDR3
SSRXI interrupt generated
Bit
Bit
Bit
7
to
to
5
2
SSRDR0
SSRDR1
Bit
SSRDR0 (MSB first transmission)
Bit
Bit
Bit
Bit
6
4
0
3
7
Bit
Bit
Bit
5
3
4
1 frame
SSRXI interrupt generated
Bit
Bit
Bit
4
2
5
Bit
Bit
Bit
3
1
6
Bit
Bit
Bit
2
7
0
SSRXI interrupt
Bit
1
generated
Bit
0