R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1098

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 22 AND/NAND Flash Memory Controller (FLCTL)
22.3.4
FLADR is a 32-bit readable/writable register that specifies an address to be output. The address of
the size specified by the command control register is output sequentially from ADR1 in byte units.
With the sector access address specification bit (ADRMD) in the command control register, it is
possible to specify whether the sector number set in the address data bits is converted into an
address to be output to the flash
• ADRMD = 1
Initial value:
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 1066 of 1650
REJ09B0313-0300
Bit
31 to 24 ADR4[7:0]
23 to 16 ADR3[7:0]
15 to 8
7 to 0
R/W:
R/W:
Bit:
Bit:
Address Register (FLADR)
R/W
R/W
Bit Name
ADR2[7:0]
ADR1[7:0]
31
15
0
0
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
All 0
All 0
All 0
All 0
R/W
R/W
28
12
ADR4[7:0]
0
ADR2[7:0]
0
memory.
R/W
R/W
27
11
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
26
10
0
0
Description
Specify 4th data to be output to flash memory as an
address when ADRMD = 1.
Specify 3rd data to be output to flash memory as an
address when ADRMD = 1.
Specify 2nd data to be output to flash memory as an
address when ADRMD = 1.
Specify 1st data to be output to flash memory as an
address when ADRMD = 1.
Fourth Address Data
Third Address Data
Second Address Data
First Address Data
R/W
R/W
25
0
9
0
R/W
R/W
24
0
8
0
R/W
R/W
23
0
7
0
R/W
R/W
22
0
6
0
R/W
R/W
21
0
5
0
R/W
R/W
20
ADR3[7:0]
0
4
ADR1[7:0]
0
R/W
R/W
19
0
3
0
R/W
R/W
18
0
2
0
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0