R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 817

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

15.5
The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI),
receive FIFO data full (RXI), and break (BRI).
Table 15.12 shows the interrupt sources and their order of priority. The interrupt sources are
enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt
request is sent to the interrupt controller for each of these interrupt sources.
When a TXI request is enabled by the TIE bit and the TDFE flag in the serial status register
(SCFSR) is set to 1, a TXI interrupt request is generated. The DMAC can be activated and data
transfer performed by this TXI interrupt request. At this time, an interrupt request is not sent to the
CPU.
When an RXI request is enabled by the RIE bit and the RDF flag or the DR flag in SCFSR is set
to 1, an RXI interrupt request is generated. The DMAC can be activated and data transfer
performed by this RXI interrupt request. At this time, an interrupt request is not sent to the CPU.
The RXI interrupt request caused by the DR flag is generated only in asynchronous mode.
When the RIE bit is set to 0 and the REIE bit is set to 1, the SCIF requests an ERI or BRI interrupt
without requesting an RXI interrupt.
The TXI indicates that transmit data can be written, and the RXI indicates that there is receive data
in SCFRDR.
Table 15.12 SCIF Interrupt Sources
Interrupt
Source
BRI
ERI
RXI
TXI
SCIF Interrupts
Description
Interrupt initiated by break (BRK) or overrun error
(ORER)
Interrupt initiated by receive error (ER)
Interrupt initiated by receive FIFO data full (RDF) or
data ready (DR)
Interrupt initiated by transmit FIFO data empty
(TDFE)
Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Sep. 28, 2009 Page 785 of 1650
DMAC
Activation
Not possible
Not possible
Possible
Possible
Priority on
Reset Release
High
Low
REJ09B0313-0300