R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1034

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 Controller Area Network (RCAN-TL1)
• Function to be implemented by software
Some of the TTCAN functions need to be implemented in software. The main details are reported
hereafter. Please refer to ISO-11898-4 for more details.
Rev. 3.00 Sep. 28, 2009 Page 1002 of 1650
REJ09B0313-0300
Cycle Time
= Time_Ref
Slave
<Configuration> Cycle Time varies between L and Time_Ref + L
<Normal Operation>
CCR = 0
⎯ Change from Init_Watch_Trigger to Watch_Trigger
⎯ Message status count
Cycle Time = 0
L
RCAN-TL1 offers the two registers TCMR0 and TCMR2 as H/W support for
Init_Watch_Trigger and Watch_Trigger respectively. The SW is requested to enable
TCMR0 and disable TCMR2 up to the first reference message is detected on the CAN Bus
and then disable TCMR0 and enable TCMR2.- Schedule Synchronization state machine.
Only reception of Next_is_Gap interrupt is supported. The application needs to take care of
stopping all transmission at the end of the current basic cycle by setting the related TXCR
flags.Master-Slave Mode control.
Only automatic cycle time synchronization and CCR increment is supported.
Software has to count scheduling errors for periodic messages in exclusive windows.
copy CCR from received time reference
CCR = 1
= Time_Ref + L
Ref_Mark and CCR are updated
at successful end of time reference reception
= L
Time_Mark 1
TTT in MB24
Time_Mark 1
TTT in MB24
Time_Mark 1
TTT in MB24
Time_Mark 2
TTT in MB25
Time_Mark 2
TTT in MB25
Time_Mark 2
TTT in MB25
Figure 19.20 Time Slave
Time_Mark 3
TTT in MB26
Time_Mark 3
TTT in MB26
Time_Mark 3
TTT in MB26
Time_Mark 4
TTT in MB27
Time_Mark 4
TTT in MB27
Time_Mark 4
TTT in MB27
Time_Mark 5
TTT in MB28
Time_Mark 5
TTT in MB28
Time_Mark 5
TTT in MB28
Time_Mark 6
TTT in MB29
Time_Mark 6
TTT in MB29
Time_Mark 6
TTT in MB29
= Time_Ref
Time_Ref
TTT in MB30
CCR isn't incremented unlike time master
Time_Ref
TTT in MB30
Time_Ref
TTT in MB30
capture timestamp
at SOF of reception
= Time_Ref + L
CCR = 0
Watch_Trigger
TCMR2