R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 711

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

13.3.2
WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the
count, overflow flags, and timer enable bit.
When used to count the clock oscillation settling time for canceling software standby mode, it
retains its value after counter overflow.
Use word access to write to WTCSR, writing H'A5 in the upper byte. Use byte access to read from
WTCSR.
Note: The method for writing to WTCSR differs from that for other registers to prevent
Bit
7
6
erroneous writes. See section 13.3.4, Notes on Register Access, for details.
Watchdog Timer Control/Status Register (WTCSR)
Bit Name
IOVF
WT/IT
Initial value:
Initial
Value
0
0
R/W:
Bit:
R/(W) R/W
IOVF
7
0
R/W
R/(W)
R/W
WT/IT
6
0
R/W
TME
Description
Interval Timer Overflow
Indicates that WTCNT has overflowed in interval timer
mode. This flag is not set in watchdog timer mode.
0: No overflow
1: WTCNT overflow in interval timer mode
[Clearing condition]
•
Timer Mode Select
Selects whether to use the WDT as a watchdog timer
or an interval timer.
0: Use as interval timer
1: Use as watchdog timer
Note: When the WTCNT overflows in watchdog timer
5
0
When 0 is written to IOVF after reading IOVF
R
4
1
-
mode, the WDTOVF signal is output externally.
If this bit is modified when the WDT is running,
the up-count may not be performed correctly.
R
3
1
-
Rev. 3.00 Sep. 28, 2009 Page 679 of 1650
R/W
2
0
CKS[2:0]
Section 13 Watchdog Timer (WDT)
R/W
1
0
R/W
0
0
REJ09B0313-0300