R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 912

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 18 Serial Sound Interface (SSI)
18.3.1
SSICR is a readable/writable 32-bit register that controls the IRQ, selects the polarity status, and
sets operating mode.
Initial value:
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 880 of 1650
REJ09B0313-0300
Bit
31 to 29
28
27
26
25
R/W:
R/W:
Bit:
Bit:
Control Register (SSICR)
SCKD SWSD SCKP SWSP SPDP
R/W
31
15
Bit Name
—
DMEN
UIEN
OIEN
IIEN
R
0
0
-
R/W
30
14
R
0
0
-
R/W
29
13
R
0
0
-
Initial
Value
All 0
0
0
0
0
DMEN
R/W
R/W
28
12
0
0
UIEN
R/W
R/W
27
11
0
0
R/W
R
R/W
R/W
R/W
R/W
OIEN
SDTA
R/W
R/W
26
10
0
0
Description
Reserved
The read value is not guaranteed. The write value
should always be 0.
DMA Enable
Enables/disables the DMA request.
0: DMA request is disabled.
1: DMA request is enabled.
Underflow Interrupt Enable
0: Underflow interrupt is disabled.
1: Underflow Interrupt is enabled.
Overflow Interrupt Enable
0: Overflow interrupt is disabled.
1: Overflow interrupt is enabled.
Idle Mode Interrupt Enable
0: Idle mode interrupt is disabled.
1: Idle mode interrupt is enabled.
PDTA
R/W
R/W
IIEN
25
0
9
0
DIEN
R/W
R/W
DEL
24
0
8
0
R/W
23
CHNL[1:0]
R
0
7
0
-
R/W
R/W
22
0
6
0
CKDV[2:0]
R/W
R/W
21
0
5
0
DWL[2:0]
R/W
R/W
20
0
4
0
MUEN
R/W
R/W
19
0
3
0
R/W
18
R
0
2
0
-
SWL[2:0]
TRMD
R/W
R/W
17
0
1
0
R/W
R/W
16
EN
0
0
0