R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 45

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Classification
Operating mode
control
System control
Symbol
MD
MD_CLK1,
MD_CLK0
ASEMD
RES
MRES
WDTOVF
BREQ
BACK
I/O
I
I
I
I
I
O
I
O
Name
Mode set
ASE mode
Power-on reset
Manual reset
Watchdog timer
overflow
request
Bus-mastership
request
acknowledge
Clock mode set
Bus-mastership
Rev. 3.00 Sep. 28, 2009 Page 13 of 1650
Function
Sets the operating mode. Do not
change the signal level on this pin
during operation.
These pins set the clock operating
mode. Do not change the signal
levels on these pins during
operation.
If a low level is input at the ASEMD
pin while the RES pin is asserted,
ASE mode is entered; if a high level
is input, product chip mode is
entered.
In ASE mode, the E10A-USB
emulator function is enabled. When
this function is not in use, fix it high.
This LSI enters the power-on reset
state when this signal goes low.
This LSI enters the manual reset
state when this signal goes low.
Outputs an overflow signal from the
WDT.
A low level is input to this pin when
an external device requests the
release of the bus mastership.
Indicates that the bus mastership
has been released to an external
device. Reception of the BACK
signal informs the device which has
output the BREQ signal that it has
acquired the bus.
Section 1 Overview
REJ09B0313-0300