R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 216

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Interrupt Controller (INTC)
Rev. 3.00 Sep. 28, 2009 Page 184 of 1650
REJ09B0313-0300
[Legend]
IRQ
Instruction (instruction replacing
interrupt exception handling)
First instruction in interrupt exception
service routine
m1:
m2:
m3:
F:
D:
E:
M:
Vector address read
Saving of SR (stack)
Saving of PC (stack)
Instruction fetch. Instruction is fetched from memory in which program is stored.
Instruction decoding. Fetched instruction is decoded.
Instruction execution. Data operation or address calculation is performed in accordance with the result of decoding.
Memory access. Memory data access is performed.
Figure 6.4 Example of Pipeline Operation when IRQ Interrupt Is Accepted
2 Icyc + 3 Bcyc + 1 Pcyc
(No Register Banking)
Interrupt acceptance
F
D
3 Icyc
3 Icyc + m1 + m2
E
E
m1
M
m2
M
m3
M
F
D
E