R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1643

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

[Legend]
I:
O:
H:
L:
Z:
K:
Notes: 1. Indicates the power-on reset by low-level input to the RES pin. The pin states after a
I/O port
H-UDI
Emulator*
Type
Input
Output
High-level output
Low-level output
High-impedance
Input pins become high-impedance, and output pins retain their state.
15
PA7 to PA0
PB12
PB11 to PB8
PB7 to PB0
PC14 to PC2, PC0
PC1
PD15 to PD0
PE15 to PE0
PF30 to PF0
TRST
TCK
TDI
TDO
TMS
AUDSYNC
AUDCK
AUDATA3 to AUDATA0
ASEBRKAK/ASEBRK
Pin Name
power-on reset by the H-UDI reset assert command or WDT overflow are the same as
the initial pin states at normal operation (see section 25, Pin Function Controller (PFC)).
Pin Function
I
O
I/O
I
I/O
I/O
I/O
I/O
I/O
I
I
I
O/Z*
I
⎯
⎯
⎯
Z
Normal
State (Other
than States
at Right)
14
Z
Z
Z
⎯
I
Z
Z*
Z*
Z
I
I
I
O/Z*
I
⎯
⎯
⎯
Z
Power-
On
Reset*
5
5
Reset State
14
1
Z
O/Z*
K/Z*
I
K/Z*
K/Z*
K/Z*
K/Z*
K/Z*
I
I
I
O/Z*
I
⎯
⎯
⎯
Z
Pin State
Retained*
Rev. 3.00 Sep. 28, 2009 Page 1611 of 1650
7
7
7
7
7
7
7
14
Pin State
2
Deep
Standby
Mode*
Z
O/Z*
K/Z*
I
K/Z*
K/Z*
K/Z*
K/Z*
K/Z*
Z
Z
Z
O/Z*
Z
⎯
⎯
⎯
Z
Power-Down State
7
7
7
7
7
7
7
14
3
Z
O/Z*
K/Z*
I
K/Z*
K/Z*
K/Z*
K/Z*
K/Z*
I
I
I
O/Z*
I
⎯
⎯
⎯
Z
Software
Standby
Mode
7
7
7
7
7
7
7
14
REJ09B0313-0300
I
O
I/O
I
I/O
I/O
I/O
I/O
I/O
I
I
I
O/Z*
I
⎯
⎯
⎯
Z
Bus
Mastership
Release
Appendix
14