R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 393

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Note:
Bus Width
32 bits
(Bus Width = 32 Bits, 16-Byte Transfer (Number of Burst 4), Wait Cycles Inserted in First
Access = 2, Wait Cycles Inserted in Second and Subsequent Access Cycles = 1)
* When the bus width is 16 bits, the access size is 16 bits, and the BST[1:0] bits in
D31 to D0
A25 to A0
CSnWCR are 10, the number of bursts and access count depend on the access start
address. At address H'xxx0 or H'xxx8, 4-4 burst access is performed. At address H'xxx4
or H'xxxC, 2-4-2 burst access is performed.
DACKn*
RD/WR
WAIT
CKIO
Figure 9.35 Burst ROM Access Timing (Clocked Asynchronous)
CSn
Access Size
8 bits
16 bits
32 bits
16 bytes
RD
BS
Note: * The waveform for DACKn is when active low is specified.
T1
Tw
CSnWCR. BST[1:0] Bits Number of Bursts Access Count
Not affected
Not affected
Not affected
Not affected
Tw
T2B
Twb
T2B
1
1
1
4
Rev. 3.00 Sep. 28, 2009 Page 361 of 1650
Twb
Section 9 Bus State Controller (BSC)
T2B
Twb
T2
1
1
1
1
REJ09B0313-0300