R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 161

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

5.2
5.2.1
Table 5.5 shows the reset-related pin configuration.
Table 5.5
5.2.2
A reset is the highest-priority exception handling source. There are two kinds of reset, power-on
and manual. As shown in table 5.6, the CPU state is initialized in both a power-on reset and a
manual reset. The FPU state is initialized by a power-on reset, but not by a manual reset. On-chip
peripheral module registers except a few registers are also initialized by a power-on reset, but not
by a manual reset.
Table 5.6
Note:
Pin Name
Power-on reset
Manual reset
Type
Power-on
reset
Manual
reset
* See section 30.3, Register States in Each Operating Mode.
Resets
Input/Output Pins
Types of Reset
RES
Low
High
High
High
High
Pin Configuration
Reset States
Conditions for Transition to Reset State
Symbol
RES
MRES
H-UDI Command
—
H-UDI reset assert
command is set
Command other
than H-UDI reset
assert is set
Command other
than H-UDI reset
assert is set
Command other
than H-UDI reset
assert is set
I/O
Input
Input
MRES
—
—
—
Low
High
Function
When this pin is driven low, this LSI shifts to the power-
on reset processing
When this pin is driven low, this LSI shifts to the manual
reset processing.
WDT Overflow
—
—
Power-on reset
—
Manual reset
Rev. 3.00 Sep. 28, 2009 Page 129 of 1650
CPU
Initialized
Initialized
Initialized
Initialized
Initialized
Section 5 Exception Handling
Internal States
Other Modules
Initialized
Initialized
*
*
*
REJ09B0313-0300