R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 435

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

10.3.4
The DMA channel control registers (CHCR) are 32-bit readable/writable registers that control the
DMA transfer mode.
The DO, AM, AL, DL, and DS bits which specify the DREQ and DACK external pin functions
can be read and written to in channels 0 to 3, but they are reserved in channels 4 to 7. The TL bit
which specifies the TEND external pin function can be read and written to in channels 0 and 1, but
it is reserved in channels 2 to 7.
Initial value:
Initial value:
Bit
31
30
Note:
R/W:
R/W:
Bit:
Bit:
*
Only 0 can be written to clear the flag after 1 is read.
DMA Channel Control Registers (CHCR)
R/W
R/W
Bit Name
TC
⎯
31
TC
15
0
0
DM[1:0]
R/W
30
14
R
0
0
-
R/W
R/W
SAR
RLD
29
13
0
0
SM[1:0]
Initial
Value
0
0
DAR
R/W
R/W
RLD
28
12
0
0
R/W
27
11
R
0
0
-
R/W
R/W
R
R/W
26
10
R
0
0
-
RS[3:0]
Description
Transfer Count Mode
Specifies whether to transmit data once or for the
count specified in DMATCR by one transfer request.
This function is valid only in on-chip peripheral module
request mode. Note that when this bit is set to 0, the
TB bit must not be set to 1 (burst mode). When the
SCIF, IIC3, SSI, FLCTL, or SSU is selected for the
transfer request source, this bit (TC) must not be set
to 1.
0: Transmits data once by one transfer request
1: Transmits data for the count specified in DMATCR
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W
25
R
0
9
0
-
by one transfer request
R/W
24
Section 10 Direct Memory Access Controller (DMAC)
R
0
8
0
-
R/W
R/W
DO
23
DL
0
7
0
Rev. 3.00 Sep. 28, 2009 Page 403 of 1650
R/W
R/W
22
DS
TL
0
6
0
R/W
21
TB
R
0
5
0
-
MASK
R/W R/(W)* R/W
R/W
20
TE
0
4
0
TS[1:0]
R/W
HE
19
0
3
0
REJ09B0313-0300
R/W R/(W)* R/W
HIE
18
IE
0
2
0
R/W
AM
17
TE
0
1
0
R/W
16
AL
DE
0
0
0