R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 537

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Notes: 1. Setting the TOCL bit to 1 prevents accidental modification when the CPU goes out of
Table 11.28 Output Level Select Function
Note: The reverse phase waveform initial output value changes to active level after elapse of the
Bit
3
2
1
0
Bit 1
OLSN
0
1
dead time after count start.
2. Clearing the TOCS0 bit to 0 makes this bit setting valid.
Bit Name
TOCL
TOCS
OLSN
OLSP
Initial Output
High level
Low level
control.
Initial
value
0
0
0
0
Low level
High level
Active Level
R/W
R/(W)* TOC Register Write Protection*
R/W
R/W
R/W
Description
This bit selects the enable/disable of write access to the
TOCS, OLSN, and OLSP bits in TOCR1.
0: Write access to the TOCS, OLSN, and OLSP bits is
1: Write access to the TOCS, OLSN, and OLSP bits is
TOC Select
This bit selects either the TOCR1 or TOCR2 setting to
be used for the output level in complementary PWM
mode and reset-synchronized PWM mode.
0: TOCR1 setting is selected
1: TOCR2 setting is selected
Output Level Select N*
This bit selects the reverse phase output level in reset-
synchronized PWM mode/complementary PWM mode.
See table 11.28.
Output Level Select P*
This bit selects the positive phase output level in reset-
synchronized PWM mode/complementary PWM mode.
See table 11.29.
Up Count
High level
Low level
enabled
disabled
Function
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Compare Match Output
Rev. 3.00 Sep. 28, 2009 Page 505 of 1650
2
2
Down Count
Low level
High level
1
REJ09B0313-0300